1. Field
The present invention relates to a receiving equalization device and a receiving equalization method.
2. Description of Related Art
A 10 Gpbs-class high-speed communication system performs transmission and reception of data via a backplane. A backplane channel for a conventional 10 Gpbs transmission may be a maximum of 40 inches, and may include a 30 inch backplane, two 3 inch daughter cards, and two 2 inch connectors. These dimensions are defined in the IEEE STD 802.3ap 10 GBASE-KR standard. Here, in a case of a single differential lane, two lines constitute a single pair, and an impedance of an entire system may be 100 ohm. A differential pair is constituted by four differential lanes, and may provide 10 Gbps per lane.
A conventional high-speed receiving equalization device may be designed based on a backplane channel, a length of which is less than or equal to 34 inches. As a length of the channel becomes longer, an effect on a channel mismatch component or an inter-symbol interference (ISI) component, such as a return loss, an insertion loss, a crosstalk, and the like, increases, and thus, a performance of the communication system may be deteriorated.
An element that most affects the backplane channel may be a near-end crosstalk (NEXT) component and a far-end crosstalk (FEXT). The two crosstalk components may cause a jitter and may affect an eye-open between transmitter and a receiver.
In general, a bit-center equalization scheme may be a scheme of obtaining a sampling timing from a part where an eye is maximally opened in an eye monitor. Another equalization scheme in the high-speed communication system that passes through a backplane environment may be a bit-edge equalization scheme. The bit-edge equalization scheme may not discover a point of a maximum eye-opening in the eye monitor, but may obtain a sampling timing by discovering a zero-crossing point.
Recently, a standard for a 40 Gpbs-class Ethernet system defined in the IEEE STD 802.3ba standard adopts an Ethernet transmission scheme that is constituted by four 10 Gpbs channels, and thus, the communication system is designed to provide 40 Gbps via 4 lanes. This is defined in the IEEE STD 802.3ba 40 GBASE-4KR standard.
In a 40 Gpbs-class multi-channel environment, namely, a four 10 Gpbs-class lanes environment, a jitter due to a mismatch of components between the channels may cause a crosstalk in the channels, efficiency of the channels may be damped less than a conventional channel, and an ISI may be generated due to crosstalk components introduced from another lane, and thus, a video quality may be deteriorated. The 802.3ba standard may have a transmission pre-equalization device having 3 taps to reduce the crosstalk components, thereby reducing the mismatch components between the channels.
However, there may be a difficulty in correcting a channel in a real communication environment by using a fixed transmission pre-equalization device having three taps based on the IEEE 802.3ba standard. Accordingly, there is a desire for an adaptive equalization method that is capable of being adaptable to a channel of a receiving end of the communication system to provide a bit error rate (BER) of 10−12.
Most of the IEEE 802.3ba standard defines a transmission equalization device to check a transmission signal based on a standard and a medium parameter, such as a cable, a printed circuit board (PCB), a trace, and the like, and does not separately define the receiving equalization device.
Accordingly, a conventional art may provide a receiving equalization method through a standard-based high-speed multi-channel backplane to a receiving end of the communication system to satisfy an electrical 40 Gpbs-class backplane Ethernet standard defined in the IEEE STD 802.3ba standard.
FIG. 1 illustrates a receiving equalization device according to a conventional art.
A jitter generated in a communication channel may prevent the receiving equalization device from obtaining an accurate value when the receiving equalization device obtains a sampling timing, thereby deteriorating a performance of a system. The deterioration of the performance of system may indicate a decrease of a performance of a BER due to a mismatch of the sampling timing. To maximize the performance of the BER, obtaining of an optimal timing is important. Accordingly, the receiving equalization device 100 obtains the sampling timing by using an eye monitor block as illustrated in FIG. 1.
The eye monitor block may obtain the sampling timing by using a bit-center scheme or a bit-edge scheme. The eye monitor block may receive a signal by using an SW and a timer at an initial time, and may obtain the sampling timing by receiving a signal corrected by the receiving equalization device 100 when the communication system is stable.
As described above, when a signal is received before equalization is performed, it is not easy for the eye monitor block to obtain an initial sampling timing by using a signal having a jitter. Thus, there is a desire for a sampling timing obtaining algorithm that may quickly and accurately obtain the sampling timing at the initial time, and may not lose the sampling timing even when another jitter component is introduced from a channel.